Ritik Vijayvergiya

Vice President at WorldQuant

Quantitative ResearchMachine LearningPythonC++Industrie 4.0 ArchitectureTeam Management

About

I'm Ritik Vijayvergiya, currently serving as Vice President at WorldQuant in Old Greenwich. My career has been defined by a deep dive into quantitative research and machine learning, moving from a researcher role to leadership within the firm. With a technical foundation from IIT Delhi in Electrical and Electronics Engineering, I’ve developed a passion for building complex systems—whether that’s ML frameworks to model user behavior or resilient IoT architectures for Industrie 4.0. Beyond the technical side, I’m interested in technology entrepreneurship and social enterprise. I’m here to connect with others in the quant and tech space to share expertise in data analysis and financial modeling, and I’m always open to discussing how emerging tech can solve large-scale business challenges.

Networking

What I can offer

  • Deep expertise in quantitative research and machine learning
  • Insights into Industrie 4.0 and IoT architectures
  • Technical leadership and team management experience

Looking for

  • expanding my professional network
  • exploring mutual opportunities in quantitative finance and machine learning

Best fit for

Quantitative researchersMachine learning engineersTech entrepreneursFinancial professionals

Current Interests

Quantitative financeMachine learningIoT architecturesTechnology entrepreneurshipSocial enterprise

Background

Career

Progressed from Quantitative Researcher to Vice President at WorldQuant over six years, following internships in data analysis at Capital One and research at Purdue University.

Education

Bachelor’s Degree in Electrical and Electronics Engineering, IIT Delhi (2014–2018); Exchange Student in Computer Science & Engineering, The University of British Columbia (2016).

Achievements

  • Promoted to Vice President at WorldQuant within four years of joining.
  • Built an ML Framework to imitate user behavior and implemented a String Kernel Algorithm for feature selection.
  • Designed resilient wireframes for industrial architectures (Industrie 4.0) for sensor-to-unit connectivity.
  • Maintained a 9.13/10 GPA at IIT Delhi.