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Pranav Jayaram

Physical Design Engineer at NXP Semiconductors

Physical DesignVLSI DesignStatic Timing Analysis (STA)SoC DesignPPA OptimizationSynthesis Techniques
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About

I'm Pranav Jayaram, a Physical Design Engineer at NXP Semiconductors in Austin. My journey in electronics began with a deep curiosity for robotics and product design, leading me through a Master’s at UT Dallas and roles at Intel and NXP. I specialize in VLSI design, specifically focusing on Static Timing Analysis and PPA optimization to push the boundaries of what SoC switch fabrics can achieve. I am passionate about cutting-edge automotive innovation, from super-integration processors to AI-powered mobility. I believe in the power of mentorship and a 'stay hungry' work ethic, and I'm always looking to connect with fellow EDA enthusiasts and industry leaders to discuss complex design challenges and the future of semiconductors.

Networking

What I can offer

  • ›Technical insights into Physical Design and VLSI
  • ›Expertise in PPA optimization and synthesis
  • ›Experience with automotive hardware and IoT-based industrial products

Looking for

  • ›expanding my professional network
  • ›exploring mutual opportunities in the semiconductor and EDA industry

Best fit for

Industry leaders and CEOs in EDASemiconductor professionalsSoC design expertsAspiring engineers seeking mentorship

Current Interests

Vehicle-integration platformsSuper-integration processors (S32N7)AI-powered mobilityElectronic Design Automation (EDA) trendsEntrepreneurship

Background

Career

Progressed from undergraduate internships in product design and robotics to a Master's in Electrical Engineering, followed by a technical internship at Intel and a full-time role in Physical Design at NXP Semiconductors.

Education

Master of Science in Electrical and Electronics Engineering from The University of Texas at Dallas (2019–2021); Bachelor of Engineering in Electrical from Dr. Ambedkar Institute of Technology (2015–2019).

Achievements

  • ›Presented 'Advanced Synthesis Techniques to Improve PPA in SoC Switch Fabric' at SNUG Converge 2026
  • ›Recipient of the National Robotics Design Challenge award at IIT-C (2016)
  • ›National Android App Development award winner at IIT-R (2016)
  • ›Developed indigenous Sp02 and bpm measurement technique using COTS components at IISc

Opinions

  • Strong drive for working on innovative cutting-edge technologies
  • Adheres to a 'hustle hard' and 'stay hungry, stay foolish' mentality
  • High value placed on technical guidance and mentorship