Naveen Kumar Rajagopal
Senior Staff Design Verification Engineer at Arteris IP
Leading design verification efforts as a Senior Staff Engineer at Arteris IP.
Intro
I'm Naveen Kumar Rajagopal, currently serving as a Senior Staff Design Verification Engineer at Arteris IP in Austin. My career has been a steady progression through the semiconductor industry, with significant tenures at Broadcom, Xilinx, and Cerium Systems. I specialize in the functional verification of SOC and IP blocks, utilizing UVM and SystemVerilog to build complex testbenches from scratch. Beyond the technical aspects of RTL design and gate-level simulation, I am deeply committed to technical leadership and the professional development of the next generation of engineers. I enjoy mentoring interns and leading teams through the intricacies of the verification lifecycle. I'm here to connect with fellow hardware professionals and explore how my expertise in VLSI and ASIC development can contribute to the evolving semiconductor landscape.
Networking
What I can offer
- ›High-level technical expertise in SOC/IP verification
- ›Leadership for managing engineering teams
- ›Mentorship for interns and junior engineers
- ›Deep knowledge of UVM and SystemVerilog
What I'm looking for
- ›expanding my professional network
- ›exploring mutual opportunities in the semiconductor and hardware engineering industry
Best fit for
Focus
Current interests
Core competencies
Background
Career
Progressed from Project Engineer at Wipro through hardware and staff engineering roles at Xilinx and Broadcom to Senior Staff leadership at Arteris IP.
Education
BE in Electronics from PES Institute of Technology Bangalore (2001 – 2005)
Achievements
- ›Successfully transitioned to Senior Staff designation at major semiconductor firms
- ›Extensive experience in TOP/Chip-level verification
- ›Built complex testbenches from the ground up
Personality
Communication style
Professional, technical, and concise with heavy use of industry-standard terminology.
Formality — 8/10
Vocabulary